Architecture

The architecture of orbit-native compute

TILE is not a commercial compute board with a radiation spec sheet. It is designed from first principles for the TID environment of LEO: deterministic inference latency, hardware SEL protection, ECC-protected memory, and a power envelope that fits a standard CubeSat EPS budget.

View Full Specs Request Briefing

Environmental design

Designed for the radiation environment

Low Earth orbit is not a clean room. Total ionizing dose, single-event effects, displacement damage — every hardware decision at Sophia Space accounts for the orbital radiation environment.

Total Ionizing Dose (TID)

30 krad(Si)

Design target for LEO at 550 km altitude over a 5-year mission lifetime. Validated against ECSS-E-ST-10-12 radiation environments.

Single-Event Effects (SEE)

SEL + SEU

Architecture incorporates single-event latchup protection and error-correcting code (ECC) memory for single-event upset mitigation without performance penalty.

Operating Temperature

−40°C to +85°C

Qualified across the thermal cycling range typical of LEO eclipse/sunlight transitions. Thermal management designed for passive conduction to the satellite structure.

Displacement Damage Dose

1×10¹⁰ n/cm²

Non-ionizing energy loss (NIEL) design target for proton and neutron displacement damage effects on optoelectronic components and memory devices.

Compute capabilities

Processing throughput matched to the workloads that matter in orbit

TILE targets the specific inference workloads satellite operators actually need: multispectral change detection, object classification on optical imagery, AIS anomaly detection for IoT passes, sensor fusion across housekeeping data. These are bounded-scope problems — not general-purpose cloud compute. A ~50 GOPS INT8 inference engine, running deterministically, is the right tool for them. A full cloud node is not.

ML inference: ONNX and TFLite model deployment. INT8 and FP16 quantized inference supported.
Memory footprint: 4 GB LPDDR4 RAM, 32 GB eMMC storage for model and result caching.
Power envelope: 8W nominal, 12W peak. Compatible with standard CubeSat EPS budgets.
Reliability: Hardware watchdog, ECC memory, scrubbing routines. Designed for unattended operation.

System architecture diagram showing satellite compute stack with processing and memory subsystems

Integration

Integrates during AIT, not after orbit insertion

TILE follows the 1U CubeSat board form factor and connects via CAN bus, SpaceWire, UART, SPI, and I²C — the interface set your bus engineers already know. Models are compiled and loaded to TILE's flash during the satellite assembly, integration, and test (AIT) phase. No orbital procedures. No new ground segment infrastructure required at launch.

Standard Interfaces

CAN bus, SpaceWire, UART, SPI, I²C — common satellite bus protocols natively supported. No custom interface hardware required.

CubeSat Form Factor

1U board form factor. Designed for 6U CubeSat minimum bus allocation. SmallSat integration available via adapter bracket.

Pre-Launch Model Loading

Operator models compiled via the TILE Toolchain and loaded to onboard flash during AIT. The toolchain converts ONNX or TFLite graphs to TILE binary format with INT8 quantization. Ground uplink for in-mission model updates is on the development roadmap — not yet available.

View Full Specifications Request Engineering Consultation