TILE by Sophia Space

Modular compute for orbit.

TILE is hardware in active development. It is designed to run your inference models, change detection algorithms, and sensor fusion pipelines — in orbit, on your satellite, processing at sensor rate before the next downlink window opens. The result is downlinked. The raw sensor data is not.

Nom. power

<500g

Mass target

Form factor

30 krad

TID tolerance

Full Specifications Request Briefing

TILE hardware compute module showing front face with connectors and board layout

Capabilities

Hardware capabilities

Radiation-Tolerant Compute

30 krad(Si) TID design target. ECC memory, SEL protection, and hardware scrubbing routines for reliable unattended operation in LEO.

On-Orbit ML Inference

ONNX and TFLite model deployment. INT8 quantized inference for change detection, classification, and anomaly detection at sensor rate.

Modular Form Factor

1U CubeSat board form factor. Designed to plug into standard 6U+ bus architectures. SmallSat adapter bracket in development.

Low Power Draw

8W nominal, 12W peak. Designed to fit within standard CubeSat electrical power system budgets without requiring a dedicated power regulator.

Standard Bus Interfaces

CAN bus, SpaceWire, UART, SPI, I²C. No proprietary interface hardware required. Designed to reduce integration overhead during satellite AIT.

Pre-Launch Model Loading

Models compiled and loaded during satellite AIT. Ground uplink for model updates is on the development roadmap for future firmware.

In development

TILE is in active hardware development

TILE is not yet in production. Engineering briefings are open with satellite operators who have upcoming missions and want to evaluate on-orbit processing during the design phase, before bus architecture is locked.

View Technical Specs Request Engineering Briefing